The skilled artisan will recognize that in microprocessor operation, exceptions arise when there is a need for the normal flow of program execution to be broken, for example, so that the processor can be diverted to handle an interrupt from a peripheral. The processor state just prior to handling the exception must be preserved so that the original program can be resumed when the exception routine has completed. Many exceptions may arise at the same time.
One common type of microprocessor is sold under the trademark ARM®, owned by Advanced RISC Machines, Ltd. (Cambridge, UK) based on an architecture set forth in the ARM Architecture Reference Manual, Version B (et. seq.), dated Jul. 26, 1996, pages 2-1 to 2-10 of which are incorporated by reference herein. (A product line of such ARM® type processors, including the SA-110™ microprocessor, is available from INTEL® Corporation (San Jose, Calif.). Such ARM® processors handle exceptions by making use of banked registers to save the processor state. The old program counter (PC) and Current Processor Status Register (CPSR) contents are copied into appropriate registers (e.g., R14 and SPSR), and the PC and mode bits in the CPSR bits are forced to a value that depends on the exception. Interrupt disable flags may be set to try and prevent otherwise unmanageable nestings of exceptions. For example, upon receiving an interrupt, the interrupt disable flags may be set to prevent new interrupts from being accepted until the current interrupt has been processed.
These ARM® processors separate interrupt handling into discrete instruction streams, i.e., one for IRQs (Interrupt Requests) and another for FIQs (Fast Interrupt Requests). The ARM® architecture generally contemplates that FIQs are to be used for relatively high priority interrupts, such as memory refresh, that are intended to run beneath the Operating System (OS). As such, FIQs are provided with a higher priority than IRQs, and may interrupt the processing of a pending IRQ exception call. In practice, however, it has been found by the inventors of the present invention that users often use FIQs as a part of a multi-tiered interrupt system usable by the OS. Disadvantageously, such use often results in complex nested interrupt stacks which the OS has difficulty, or is unable, to ‘unwind’ and properly process these interrupts. As a result, the OS is often unable to support calls from both IRQ and FIQ devices.
Thus, a need exists for an improved method and system for providing a single interrupt instruction stream for both multiple (e.g., IRQ and FIQ) exceptions.